/*
 * Copyright (c) Huawei Technologies Co., Ltd. 2023-2023.
 * Description: sched clock tolerance clock async interface.
 * Author: wanglinhui <wanglinhui@huawei.com>
 * Create: 2023-09-21
 */
#include <linux/jiffies.h>
#include <internal/sched_clock_tolerance.h>

static u64 delta_interval;
static u64 (*sched_clk_regis_read)(void);

static u64 read_reim(void)
{
	return sched_clk_regis_read() - delta_interval;
}

void update_read(u64 (**read_ptr)(void), u32 mult, u32 shift)
{
	u64 jiffy_ns;
	u64 tmp;

	/* 1 jiffiy is an empirical value. Assume that the clock of
	 * the CPU is not synchronized in time, the maximum clock
	 * differences does not exceed 1 jiffiy.
	 */
	jiffy_ns = jiffies_to_nsecs(1);
	tmp = jiffy_ns << shift;
	do_div(tmp, mult);

	delta_interval = tmp;
	sched_clk_regis_read = *read_ptr;
	*read_ptr = read_reim;
}
